In a manufacturing process of a semiconductor device or an FPD (flat panel display), a plasma is often used in processes, e.g., etching, deposition, oxidation, sputtering and the like, in order to allow a processing gas to react efficiently at a relatively low temperature. Conventionally, a capacitively coupled plasma processing apparatus is mainly used for a single-wafer plasma processing apparatus, especially a single-wafer plasma etching apparatus.
Generally, in the capacitively coupled plasma processing apparatus, an upper and a lower electrode are disposed in parallel with each other in a processing chamber as a vacuum chamber, and a target substrate (e.g., a semiconductor wafer, a glass substrate or the like) is mounted on the lower electrode. In that state, a radio frequency (RF) voltage is applied between the electrodes, and electrons are accelerated by an electric field formed between the electrodes by the application of the RF voltage. Plasma is generated due to ionization by collision between the electrons and the processing gas, and a desired microprocessing, e.g., etching, is performed on a substrate surface by radicals or ions in the plasma.
Along with the recent trend for miniaturization of a design rule in manufacturing a semiconductor device or the like, the high dimensional accuracy is required especially in the plasma etching and, hence, selectivity against an etching mask and an underlying layer and/or in-plane uniformity in the etching need to be improved. Accordingly, there arises a demand for low ion energy and low pressure in a processing region inside a chamber. For that reason, a RF power of about 40 MHz or greater has been used, which is significantly higher than that in a conventional case.
However, the low pressure and low ion energy causes charging damage that has not occurred conventionally. That is, in the conventional apparatus having high ion energy, in-plane distribution of a plasma potential does not cause a critical problem. However, if the ion energy decreases at a lower pressure, the in-plane non-uniformity of the plasma potential easily causes charging damage of a gate oxide film.
Further, in a plasma process using a RF power of a high frequency, e.g., 40 MHz or greater, it is a general trend that the etching rate at a central portion of a wafer becomes higher and the etching rate at a peripheral portion of the wafer becomes lower.
To that end, Japanese patent Laid-open Publication No. 2001-185542 and corresponding U.S. Pat. No. 6,624,084 describe an equipment including a current path correction means for correcting a current path part near an outer periphery of a wafer among RF current paths formed by a RF bias applied to the wafer so as to face a wafer facing surface of an opposite electrode or an impedance adjustment means for making am impedance up to a ground viewed from the RF bias almost uniform in the wafer surface. Accordingly, wafer in-plane uniformity of a self-bias generated by the RF bias application can be improved and, also, macro damage can be suppressed.
However, the technique disclosed in Japanese patent Laid-open Publication No. 2001-185542 and the corresponding U.S. Pat. No. 6,624,084 is disadvantageous in that the presence of the current path correcting means or the impedance adjustment means makes the equipment configuration complicated, and also in that the in-plane uniformity of the plasma processing may be insufficient.
Besides, in the plasma processing, there may occur charging damage as follows. The charge-up of the gate oxide film is caused by a local electric field produced by unbalance between ions and electrons in the wafer surface, which leads to dielectric breakdown. For example, in the plasma etching, the ions are injected perpendicularly to the main surface of the wafer, whereas the electrons are injected thereto at an inclined angle. Accordingly, the balance of charges is locally disturbed, and charge-up occurs in random locations. The charging damage depends on a profile of an etching pattern as well as in-plane uniformity of a self-bias, and occurs in random locations. Therefore, the problem of charging damage cannot be effectively solved by the technique described in Japanese patent Laid-open Publication No. 2001-185542 and the corresponding U.S. Pat. No. 6,624,084.